1. Technical Field
The present invention relates generally to semiconductor technology, and more specifically to shallow junction formation in semiconductor integrated circuit devices.
2. Background Art
At the present time, electronic products are used in almost every aspect of life, and the heart of these electronic products is the integrated circuit. Integrated circuits are used in everything from airplanes and televisions to wristwatches.
Integrated circuits are made in and on silicon wafers by extremely complex systems that require the coordination of hundreds or even thousands of precisely controlled processes to produce a finished semiconductor wafer. Each finished semiconductor wafer has hundreds to tens of thousands of integrated circuits, each wafer worth hundreds or thousands of dollars.
Integrated circuits are made up of hundreds to millions of individual components. One common component is the semiconductor transistor. The most common and important semiconductor technology presently used is silicon-based, and the most preferred silicon-based semiconductor device is a Complementary Metal Oxide Semiconductor (“CMOS”) transistor.
The principal elements of a CMOS transistor generally consist of a silicon substrate having shallow trench oxide isolation regions cordoning off transistor areas. The transistor areas contain polysilicon gates on silicon oxide gates, or gate oxides, over the silicon substrate. The silicon substrate on both sides of the polysilicon gate is slightly doped to become conductive. These lightly doped regions of the silicon substrate are referred to as “shallow source/drain junctions”, which are separated by a channel region beneath the polysilicon gate. A curved silicon oxide or silicon nitride spacer, referred to as a “sidewall spacer”, on the sides of the polysilicon gate allows deposition of additional doping to form more heavily doped regions of the shallow source/drain (“S/D”) junctions, which are called “deep S/D junctions”. The shallow and deep S/D junctions together are collectively referred to as “S/D junctions”.
To complete the transistor, a silicon oxide dielectric layer is deposited to cover the polysilicon gate, the curved spacer, and the silicon substrate. To provide electrical connections for the transistor, openings are etched in the silicon oxide dielectric layer to the polysilicon gate and the S/D junctions. The openings are filled with metal to form electrical contacts. To complete the integrated circuits, the contacts are connected to additional levels of wiring in additional levels of dielectric material to the outside of the dielectric material.
In operation, an input signal to the gate contact to the polysilicon gate controls the flow of electric current from one S/D contact through one S/D junction through the channel to the other S/D junction and to the other S/D contact.
Transistors are fabricated by thermally growing a gate oxide layer on the silicon substrate of a semiconductor wafer and forming a polysilicon layer over the gate oxide layer. The oxide layer and polysilicon layer are patterned and etched to form the gate oxides and polysilicon gates, respectively. The gate oxides and polysilicon gates in turn are used as masks to form the shallow S/D regions by ion implantation of boron or phosphorus impurity atoms into the surface of the silicon substrate. The ion implantation is followed by a high-temperature anneal above 700° C. to activate the implanted impurity atoms to form the shallow S/D junctions.
A silicon nitride layer is deposited and etched to form sidewall spacers around the side surfaces of the gate oxides and polysilicon gates. The sidewall spacers, the gate oxides, and the polysilicon gates are used as masks for the conventional S/D regions by ion implantation of boron or phosphorus impurity atoms into the surface of the silicon substrate into and through the shallow S/D junctions. The ion implantation is again followed by a high-temperature anneal above 700° C. to activate the implanted impurity atoms to form the S/D junctions.
After formation of the transistors, a silicon oxide dielectric layer is deposited over the transistors and contact openings are etched down to the S/D junctions and to the polysilicon gates. The contact openings are then filled with a conductive metal and interconnected by formation of conductive wires in other interlayer dielectric (“ILD”) layers.
As transistors have decreased in size, it has been found that the electrical resistance between the metal contacts and the silicon substrate or the polysilicon has increased to the level where it negatively impacts the performance of the transistors. To lower the electrical resistance, a transition material is formed between the metal contacts and the silicon substrate or the polysilicon. The best transition materials have been found to be cobalt silicide (CoSi2) and titanium silicide (TiSi2).
The silicides are formed by first applying a thin layer of the cobalt or titanium on the silicon substrate above the S/D junctions and the polysilicon gates. The semiconductor wafer is subjected to one or more annealing steps at temperatures above 800° C. and this causes the cobalt or titanium to selectively react with the silicon and the polysilicon to form the metal silicide. The process is generally referred to as “siliciding”. Since the shallow trench oxide and the sidewall spacers will not react to form a silicide, the silicides are aligned over the S/D junctions and the polysilicon gates so the process is also referred to as “self-aligned siliciding”, or “saliciding”.
Salicidation technology is vital for improving the operating speed of modem semiconductor devices with sub-micron feature sizes. The salicide technology is widely use to increase the packing density of integrated circuits and to reduce the circuit interconnect resistance for high-speed operation. With the continuous decrease in device sizes (transistors becoming narrower and thinner and transistor channels becoming shorter), salicidation problems like junction punchthrough, current leakage, and contact resistance continue to reduce product yields and reliability.
In general, salicidation results in high junction leakage due to metal penetration into the silicon substrate. The penetration of the metal “spikes” the junction, causing the current leakage.
Residual metal from the salicidation process can also cause leakage. The silicide across the sidewall spacers may not be totally removed after the salicidation. The residual metal can cause a bridge between adjacent circuit features, like the gate and the S/D regions, causing current leakage.
Nevertheless, as device dimensions continue to be scaled to smaller and smaller dimensions, it is necessary to scale down extension junction depths as well. Furthermore, shallow junctions are increasingly needed to control adverse charge-sharing effects (two dimensional short channel effects) in advanced devices such as metal oxide field effect transistors. Extended ultra-shallow S/D junctions can improve such negative effects, can suppress the short channel effect, and can improve device operating speeds.
However, existing shallow S/D junction fabrication technologies, such as ion implantation followed by rapid thermal annealing, have not succeeded in solving all the problems related to fabricating increasingly shallow S/D junctions, and to connecting metal contacts to them.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.